Switch-Level Timing Simulation of MOS VLSI (Metal-Oxide-Semiconductor Very Large-Scale Integrated) Circuits
Author | : Vasant B. Rao |
Publisher | : |
Total Pages | : 246 |
Release | : 1985 |
ISBN-10 | : OCLC:227661643 |
ISBN-13 | : |
Rating | : 4/5 ( Downloads) |
Download or read book Switch-Level Timing Simulation of MOS VLSI (Metal-Oxide-Semiconductor Very Large-Scale Integrated) Circuits written by Vasant B. Rao and published by . This book was released on 1985 with total page 246 pages. Available in PDF, EPUB and Kindle. Book excerpt: This report deals with the development of a fast and accurate simulation tool for very-large-scale integrated (VLSI) circuits consisting of metal-oxide-semiconductor (MOS) transistors. Such tools are called switch-level timing simulators and they provide adequate information on the performance of the circuits with a reasonable expenditure of computation time even for very large circuits. The algorithms presented in this thesis can handle only n-channel MOS(NMOS) circuits, but are easily extendible to handle complementary MOS(CMOS) circuits as well. The algorithms presented in this report have been implemented in a computer program called MOSTIM. In all the circuits simulated thus far, MOSTIM provides timing information with an accuracy of within 10% of that provided by SPICE2, at approximately two orders of magnitude faster in simulation speed. (Author).